The present invention relates to a data communication method in a shared memory multiprocessor system and, in particular, to realizing data communication with coherence being maintained and speed-up of such data communication, and further to a coherence control.
In a shared memory multiprocessor system where a plurality of processors share a memory, it is necessary to communicate shared data between the processors upon executing parallel programs.
Conventionally, when performing communication of the shared data, a process called a lock process has been executed for maintaining coherence.
This process is a process for executing an exclusive control of data to allow one of the processors to exclusively read/write data shared by the processors.
The exclusive control can avoid an occurrence of wrong processing wherein, for example, the plurality of processors read/write simultaneously so that a readout value of data differs depending on order of access.
For realizing the exclusive control, a test and set instruction or the like provided for the processors is normally used.
The test and set instruction (1) reads out data, which is stored at a certain address on a memory, into a register; (2) writes a value “1” into the memory at the same address; and (3) determines whether a value read out into the register is “0”.
The test and set instruction ensures inseparable execution of the foregoing operations (1) to (3) without being influenced or interrupted from the other processors during the execution thereof.
Only when the value read out into the register by the test and set instruction is “0”, the subject processor determines that the exclusive control is realized, so that the subsequent exclusive control performs necessary processing.
After this processing is finished, this processor writes a value “0” into the memory at the same address, thereby to allow the other processors to realize the exclusive control.
On the other hand, if the value read out into the register by the test and set instruction is “1”, the subject processor, determining that the exclusive control is not realized, executes again the test and set instruction, and then repeats it until a value read out into the register becomes “0”.
The exclusive control using the test and set instruction is described in Kisaburo Nakazawa, “Computer Architecture and Configuration Method”, Asakura Bookstore, November 1995, pp.388–389.
It is time-consuming to perform the data communication with coherence being maintained between the processors by executing the exclusive control based on the conventional lock process.
Particularly, when data transfer is frequently required, the processing speed may be largely lowered due to influence of the lock process.
This is caused by the fact that the lock process always requires data read/write processing on a main memory so that every execution of the test and set instruction requires much time.
Further, since the data read/write processing on the main memory based on the lock process is executed with respect to one same address, lowering of the memory access performance may be induced.